The invention relates generally to frequency synthesis and more particularly, to fractional-N frequency synthesizers.
A frequency synthesizer generates an output signal having a frequency which has some relationship to a reference frequency, the accuracy of the output signal frequency typically being determined by the accuracy and stability of the source of the reference frequency. Frequency synthesizers utilizing a phase lock loop (PLL) to provide an output signal are well known in the art. Typically, a PLL includes a tunable oscillator, such as a voltage controlled oscillator (VCO), the output (f.sub.0) of which is locked to the known reference signal (f.sub.r) by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the reference signal and the VCO output signal. The output of the phase comparator is coupled to the input of the VCO through a loop filter to tune and lock the VCO to a desired frequency.
To provide signals having different output frequencies, the PLL frequency synthesizer typically includes a controllable divider circuit interposed between the output of the VCO and the phase comparator. A processor receives the user's frequency selection and controls the divider circuit to divide the frequency of the VCO output signal by an appropriate number before providing the VCO output signal to the phase comparator. The frequency of the VCO output signal can thus be a multiple of the reference frequency. To obtain divisors which are greater than the value of the divider circuit, a divider period of multiple cycles is established over which the divisor value is averaged. While the divisor value is low in any particular cycle, when averaged over the entire period, the divisor value is correct. For example, where a divisor of 103 is required and the divider divides by the value of 10 or by 11, the processor of the synthesizer may command the divider to divide the VCO output frequency by ten for seven cycles of the period and by eleven for three cycles of the same period. Thus, when averaged over the entire period of ten cycles, the divisor of 103 is realized.
The output frequency f.sub.0 of the VCO is thus related to the frequency f.sub.r of the reference frequency source by the relationship: EQU f.sub.o +N*f.sub.r
where N=the ratio desired between output and reference frequencies.
Typically, divider circuits divide only by integers and the smallest increment of change .DELTA. in the VCO output frequency (.DELTA.f.sub.o) is equal to the reference frequency itself (f.sub.r). Therefore, the change in N (.DELTA.N) must be equal to or greater than one. This can result in a limitation on the frequency resolution of the synthesizer unless a very low reference frequency is used to achieve small increments of frequency change. However, a low reference frequency, or small step size, introduces undesirable effects such as a long settling time for the PLL and a higher noise level.
A technique known as fractional-N synthesis has been used to synthesize output signals at a frequency that is any arbitrary fraction of the reference signal frequency thereby permitting use of reference frequency sources having higher frequencies. Increments of frequency change in the output signal may be smaller than the frequency of the reference source.
In one technique, fractional division is simulated by changing the divisor value temporarily during the course of a second period which is longer than the first division period discussed above. Non-integer division ratios are realized by dividing by N+1, for example, instead of N, on a proportional number of division cycles of the second period to provide the desired divisor number when averaged over that second period. For example, if the desired divisor is N.1, the divide value will be N for nine division cycles and N+1 for one division cycle of the ten division cycles. Thus, when averaged over the entire second period of ten cycles, the divisor factor equals N.1 and the VCO output frequency will be N.1 times the reference frequency. To achieve this N+F/K divisor, the divider circuit will divide K-F cycles by N and F cycles by N+1, where K=the increase in periodicity and F&gt;0 but smaller than K. Applying this to the example of N.1 above, F=1 and K=10.
Applying this to the rational division example above, N would be 103. To obtain the divisor of 103.1, the divisor of 103 would be applied for nine cycles and the divisor of 104 would be applied for one cycle. When averaged over the entire ten cycles of the second period, the divisor of 103.1 results. Two periods exist in this example. The first is the basic division period of ten cycles in which the divisor averages 103. The second period is longer than the first and in this case, includes ten of the first periods. When averaged over this second period, the divisor averages 103.1.
A common method of achieving such fractional division in a fractional-N synthesizer is through the use of an accumulator. An example of such a prior art system is shown in FIG. 1. The synthesizer 10 of FIG. 1 includes a reference oscillator 12 which provides a reference frequency signal to a dual modulo counter 14. In this case, the dual modulo counter divides the frequency of the input signal by N or N+1 as selected. The divided signal is provided then to a programmable delay generator 16 which provides the output signal F.sub.o. A digital divider 20 receives the output signal frequency selection from the user and determines the correct divisor to achieve the selected output frequency. This divisor is input to the modulo counter 14 over line 22. The digital divider 20 also inputs the incrementing value to the accumulator 26 over line 24. The accumulator 26 provides the value of its contents to the programmable delay generator 16. Output pulses from the programmable delay generator 16 increment the accumulator. At the time that the accumulator increments to its overflow, its carry signal is provided to the modulo counter 14 which then divides by N+1 instead of N.
The synthesizer 10 of FIG. 1 is directed to producing an output frequency which is less than the reference frequency 12. For example, in the case where the reference frequency F.sub.r is 10 Mhz and the desired output frequency F.sub.o is 3 Mhz, the digital divider 20 determines that one pulse should be produced by the synthesizer 10 for each 3.3333 pulses from the reference oscillator 12. The modulo counter 14 is thus set to selectably divide by three (N) and by four (N+1). The combination of dividing and delay results in an output frequency F.sub.o of 3 mhz. Such a synthesizer is disclosed in further detail in U.S. Pat. No. 3,976,945 to Cox.
One disadvantage of prior accumulator-based systems is the lack of flexibility. Once an accumulator has been installed and the overflow and increment values have been selected, it is relatively difficult to change these values. For example, once an accumulator has been installed which accumulates to sixteen before overflowing, it is difficult to change it to overflow at fifteen or at seventeen. Attempts to permit easier alteration of these values after installation of the accumulator typically include additional hardware devices to exert some control over the accumulator operation. The addition of such devices results in increased complexity, increased expense, larger size, and slower response times.
Some applications would benefit from a more easily programmable fractionality control technique; one which does not require additional hardware devices and control circuits to enable such programmability. For example, in some prior synthesizers, a multiplier is switched into the output circuit when the user selects a frequency residing in a higher range of frequencies. The multiplier not only increases the output frequency but also increases the step size by the multiplier value. In such synthesizers, the step size is maintained at the pre-multiplier step size by switching in an additional divider circuit at the time that the multiplier circuit is switched in. This approach adds complexity and additional hardware.
A fractionality control apparatus having the ability to change the step size or fraction simply by a processor command would be desirable. A fractional control apparatus which could as easily provide the fraction of 1/7 as it could provide 1/57 would enable much greater control over the frequency resolution of the output signal. If such an apparatus were available, the same fractionality control circuit could be used in synthesizers manufactured for different applications. The fractionality control apparatus could be programmed for the particular application prior to delivery, or at another time. Additionally, applications exist where widely varying fractions are desired and having a dynamic fractionality control apparatus which can select such fractions in response to processor control during synthesizer operation would satisfy such an application.
Hence, those concerned with providing fractional-N frequency synthesizers have recognized a need for a more flexible and versatile synthesizer, one which can provide greater flexibility in controlling fractionality without requiring complex fractionality circuits or hardware replacement. The present invention fulfills this need.